VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic

An adiabatic logic is a technique to design low power digital VLSI’s. This paper describes the design and VLSI implementation of a multiplier using a two phase drive adiabatic dynamic CMOS logic (2PADCL) circuit. Circuit operation and performance have been evaluated using a 4×4-bit 2PADCL multiplier fabricated in a 1.2 μm CMOS process. The experimental results show that the multiplier was operated with clock frequencies 800 kHz. The total power dissipation of the 4 × 4-bit 2PADCL multiplier was also 5.19 mW at the 1.5 V DC power supply voltage. key words: adiabatic logic, multiplier, low power, two-phase power supply